SN74LS673N

Feature

·16-Bit Serial-In,Serial-Out Shift Register with 16-Bit Parallel-Out Storage Register
·Performs Serial-to-Parallel Conversion

Description
The ' LS673 is a 16-bit shift register and a 16-bit storage register in a single 24-pin package.A three-state input/output (SER/Q15) port to the shift register allows serial entry and/or reading of data. The storage register is connected in a parallel data loop with the shift register and may be asynchronously cleared by taking the store-clear input low. The storage register may be parallel loaded with shift-register data to provide shift-registerstatus via the parallel outputs. The shift register can be parallel loaded with the storage-register data upon command.
A high logic level at the chip-level(CS) input disablesboth the shift-register clock and the storage register clock and places SER/Q15 in the high-impedance state.
The store-clear function is not disabled by the chip select.
Caution must be exercised to prevent false clocking of either the shift register or the storage register via the chip-select input. The shift clock should be low during the low-to-high transition of chip select and the store clock should be low during the high-to-low transition of chip select.

Feature

(Picture: Pinout)