The CD40109, unlike other low-to-high level-shifting circuits, does not require the presence of the high-voltage supply(VoD) before the application of either thelow-voltage supply (Vcc) or the input signals. There are no restrictions on the sequence of application of Vop, Vcc, or the input signals. In addition, with one exception there are no restrictions on therelative magnitudes of the supply voltagesor input signals within the device maximum ratings, provided that the input signal swings between Vss and at least 0.7 Vcci Vccmay exceed Voo, and input signals mayexceed Vcc and Vop-When operated in the mode Vcc>Voo, the CD40109 will operate as a high-to-low level-shifter.
The CD40109 also features individual three-state output capability.A low level on any of the separately anabled three-state output controls produces ahigh-impedance-state in the corretponding output.
The CD40109B-Series types are supplied in 16-lead ceramic dual-in-line packages (F3A suffix),16-lead dual-in-line plastic packages(E suffix),16-lead small-outline packages(NSR suffix), and 16-lead thin shrinksmall-outline packages(PW and PWR suffixes).
Applications:
Ichor-low levl-thifting with thrse-atrte outpurts for unidirectional or bidirectiont busting
lsolation of logie subeystems using sopar.ate power supplies from supply ioqvanc-ine.tupply los and supply redation comaiderations
Features:
Indapendenoe of power upply swquence contiderationt-Vcc can axooed Vop. input ionals can axcaed both Vcc and Voo
· Up and down lovel-thifting capability
· Three state outputs with swperate anable controls
· Standardized, tymmatrical output cheractaerintics
·100% twutad for quietcant current at 20V
· Maximum input current of 1 gA at 18V over full package-temperature rangs;
100nA at 18 Vand 250℃
. Nolne margin (futl package-tamperature range)
-1Vat Vcc"5 V, VDD-10V
=2V at Vcc=10V, VDp=15V
·5-V,10V, and 15-V parametrie ratings
· Meote all requlraments of JEDEC Tentative Stundand No,138."Standand Sooclilcatdons for Doncrlpltion of"B' Sorien ClMiOS Davtcas"
Feature
- Independence of power supply sequence considerations - VCC can exceed VDD, input signals can exceed both VCC and VDD
- Up and down level-shifting capability
- Three-state outputs with separate enable controls
- Standardized, symmetrical output characteristics
- 100% tested for quiescent current at 20 V
- Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
- Noise margin (full package-temperature range):
= 1 V at VCC = 5 V, VDD = 10 V
= 2 V at VCC = 10 V, VDD = 15 V - 5-V, 10-V, and 15-V parametric ratings
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
- Applications:
- High-or-low level-shifting with three-state outputs for unidirectional or bidirectional bussing.
- Isolation of logic subsystems using separate power supplies from supply sequencing, supply loss and supply regulation considerations
(Picture:Pinout / Diagram)
