General Description
The S25FL032P is a 3.0 V (2.7 V to 3.6 V), single-power-supply Flash memory device. The device consists of 64 uniform 64-KB sectors with the two (top or bottom) 64-KB sectors further split up into thirty-two 4-KB sub sectors. The S25FL032P device is fully backward compatible with the S25FL032A device. The device accepts data written to Serial Input (SI) and outputs data on Serial Output (SO). The devices are designed to be programmed in-system with the standard system 3.0-V VCC supply. The S25FL032P device adds the following high-performance features using five new instructions: Dual Output Read using both SI and SO pins as output pins at a clock rate of up to 80 MHz Quad Output Read using SI, SO, W#/ACC, and HOLD# pins as output pins at a clock rate of up to 80 MHz Dual I/O High Performance Read using both SI and SO pins as input and output pins at a clock rate of up to 80 MHz Quad I/O High Performance Read using SI, SO, W#/ACC, and HOLD# pins as input and output pins at a clock rate of up to 80 MHz Quad Page Programming using SI, SO, W#/ACC, and HOLD# pins as input pins to program data at a clock rate of up to 80 MHz The memory can be programmed 1 to 256 bytes at a time, using the Page Program command. The device supports Sector Erase and Bulk Erase commands. Each device requires only a 3.0-V power supply (2.7 V to 3.6 V) for both read and write functions. Internally generated and regulated voltages are provided for the program operations. This device requires a high voltage supply to the W#/ACC pin to enable the Accelerated Programming mode. The S25FL032P device also offers a One-Time Programmable area (OTP) of up to 128 bits (16 bytes) for permanent secure identification and an additional 490 bytes of OTP space for other use. This OTP area can be programmed or read using the OTPP or OTPR instructions.
Architectural Advantages
Single power supply operation
– Full voltage range: 2.7 V to 3.6 V read and write operations
Memory architecture
– Uniform 64-KB sectors
– Top or bottom parameter block (two 64-KB sectors (top or bottom) broken down into 16 4-KB sub-sectors each)
– 256-byte page size
– Backward compatible with the S25FL032A device
Program
– Page Program (up to 256 bytes) in 1.5 ms (typical)
– Program operations are on a page by page basis
– Accelerated programming mode via 9-V W#/ACC pin
– Quad Page Programming
Erase
– Bulk erase function
– Sector erase (SE) command (D8h) for 64-KB sectors
– Sub-sector erase (P4E) command (20h) for 4-KB sectors
– Sub-sector erase (P8E) command (40h) for 8-KB sectors
Cycling endurance – 100,000 cycles per sector typical
Data retention
– 20 years typical
Device ID
– JEDEC standard two-byte electronic signature
– RES command one-byte electronic signature for backward compatibility
One time programmable (OTP) area for permanent, secure identification; can be programmed and locked at the factory or by the customer
Common Flash Interface (CFI) compliant: allows host system to identify and accommodate multiple flash devices
Process technology – Manufactured on 0.09
m MirrorBit® process technology
Package option
– Industry Standard Pinouts
– 8-pin SO package (208 mils)
– 16-pin SO package (300 mils)
– 8-contact USON package (5 6 mm)
– 8-contact WSON package (6 8 mm)
– 24-ball BGA 6
8 mm package, 5
5 pin configuration
– 24-ball BGA 6
8 mm package, 6
4 pin configuration Performance Characteristics
Speed
– Normal READ (Serial): 40-MHz clock rate
– FAST_READ (Serial): 104-MHz clock rate (maximum)
– DUAL I/O FAST_READ: 80-MHz clock rate or 20 MB/s effective data rate
– QUAD I/O FAST_READ: 80 MHz clock rate or 40 MB/s effective data rate
Power saving standby mode
– Standby Mode 80
A (typical)
– Deep Power-Down Mode 3
A (typical) Memory Protection Features
Memory protection
– W#/ACC pin works in conjunction with Status Register Bits to protect specified memory areas
– Status Register Block Protection bits (BP2, BP1, BP0) in status register configure parts of memory as read-only
(Picture: Pinout)
