GENERAL
• Supports Serial Peripheral Interface -- Mode 0 and Mode 3
• 33,554,432 x 1 bit structure
or 16,777,216 x 2 bits (two I/O read mode) structure
or 8,388,608 x 4 bits (four I/O mode) structure
• 1024 Equal Sectors with 4K bytes each
- Any Sector can be erased individually
• 128 Equal Blocks with 32K bytes each
- Any Block can be erased individually
• 64 Equal Blocks with 64K bytes each
- Any Block can be erased individually
• Power Supply Operation
- 2.65 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
PERFORMANCE
• High Performance
VCC = 2.65 to 3.6V
- Normal read
- 50MHz
- Fast read
- FAST_READ, DREAD, QREAD: 133MHz with 8 dummy cycles
- 2READ:
104MHz with 4 dummy cycle,
133MHz with 8 dummy cycle
- 4READ:
104MHz with 6 dummy cycle,
133MHz with 10 dummy cycle
- Configurable dummy cycle number for 2READ and 4READ operation
- 8/16/32/64 byte Wrap-Around Burst Read Mode
• Low Power Consumption
• Typical 100,000 erase/program cycles
• 20 years data retention
KEY FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- Block Lock Protection
The BP0-BP3 and T/B status bits define the site of the area to be protected against program and erase instructions.
• Additional 4K bits secured OTP
- Features unique identifier
- Factory locked identifiable and customer lockable
• Auto Erase and Auto Program Algorithms
- Automatically erases and verifies data at selected sector
- Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse width (Any page to be programmed should have page in the erased state first.)
• Status Register Feature
• Command Reset
• Program/Erase Suspend
• Program/Erase Resume
• Electronic Identification
- JEDEC 1-byte Manufacturer ID and 2-byte Device ID
- RES command for 1-byte Device ID
• Support Serial Flash Discoverable Parameters (SFDP) mode
- All devices are RoHS Compliant and Halogen free
2. GENERAL DESCRIPTION
MX25L3233F is 32Mb bits Serial NOR Flash memory, which is configured as 4,194,304 x 8 internally. When it is
in four I/O mode, the structure becomes 8,388,608 bits x 4. When it is in two I/O mode, the structure becomes
16,777,216 bits x 2.
MX25L3233F features a serial peripheral interface and software protocol allowing operation on a simple 3-wire
bus while it is in single I/O mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and a
serial data output (SO). Serial access to the device is enabled by CS# input.
MX25L3233F, MXSMIO® (Serial Multi I/O) flash memory, provides sequential read operation on the whole chip and multi-I/O features.
When it is in quad I/O mode, the SI pin, SO pin, WP# pin and HOLD# pin become SIO0 pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data Input/Output.
After program/erase command is issued, auto program/erase algorithms which program/erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256 bytes) basis. Erase command is executed on 4K-byte sector, 32K-byte/64K-byte block, or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit.
When the device is not in operation and CS# is high, it is put in standby mode.
The MX25L3233F utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after
100,000 program and erase cycles.
(Picture: Pinout)
