The Cypress S25FL512S device is a flash nonvolatile memory product using:
- MirrorBit technology - that stores two data bits in each memory array transistor
- Eclipse architecture - that dramatically improves program and erase performance
- 65 nm process lithography
This device connects to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output (Single I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit (Quad I/O or QIO) serial commands. This multiple width interface is called SPI Multi-I/O or MIO. In addition, the FL-S family adds support for Double Data Rate (DDR) read commands for SIO, DIO, and QIO that transfer address and read data on both edges of the clock.
The Eclipse architecture features a Page Programming Buffer that allows up to 256 words (512 bytes) to be programmed in one operation, resulting in faster effective programming and erase than prior generation SPI program or erase algorithms.
Executing code directly from flash memory is often called Execute-In-Place or XIP. By using FL-S devices at the higher clock rates supported, with QIO or DDR-QIO commands, the instruction read transfer rate can match or exceed traditional parallel interface, asynchronous, NOR flash memories while reducing signal count dramatically.
The S25FL512S product offers high densities coupled with the flexibility and fast performance required by a variety of embedded applications. It is ideal for code shadowing, XIP, and data storage.
Features
- CMOS 3.0 Volt Core with versatile I/O
- Serial Peripheral Interface (SPI) with Multi-I/O
- Density
- 512 Mbits (64 Mbytes)
- SPI
- SPI Clock polarity and phase modes 0 and 3
- Double Data Rate (DDR) option
- Extended Addressing: 32-bit address
- Serial Command set and footprint compatible with S25FL-A, S25FL-K, and S25FL-P SPI families
- Multi I/O Command set and footprint compatible with the S25FL-P SPI family
- READ Commands
- Normal, Fast, Dual, Quad, Fast DDR, Dual DDR, Quad DDR
- AutoBoot - power up or reset and execute a Normal or Quad read command automatically at a preselected address
- Common Flash Interface (CFI) data for configuration information.
- Programming (1.5 MBps)
- 512-byte Page Programming buffer
- Quad-Input Page Programming (QPP) for slow clock systems
- Automatic ECC -internal hardware Error Correction Code generation with single bit error correction
- Erase (0.5 to 0.65 MBps)
- Uniform 256-kbyte sectors
- Cycling Endurance
- 100,000 Program-Erase Cycles, minimum
- Data Retention
- 20-Year Data Retention, minimum
- Security features
- OTP array of 1024 bytes
- Block Protection:
- Status Register bits to control protection against program or erase of a contiguous range of sectors.
- Hardware and software control options
- Advanced Sector Protection (ASP)
- Individual sector protection controlled by boot code or password
- Cypress® 65 nm MirrorBit® Technology with Eclipse™ Architecture
- Core supply voltage: 2.7 V to 3.6 V
- I/O supply voltage: 1.65 V to 3.6 V
- SO16 and FBGA packages
- Temperature range:
- Industrial (–40 °C to +85 °C)
- Industrial Plus (–40 °C to +105 °C)
- Automotive, AEC-Q100 Grade 3 (–40 °C to +85 °C)
- Automotive, AEC-Q100 Grade 2 (–40 °C to +105 °C)
- Automotive, AEC-Q100 Grade 1 (–40 °C to +125 °C)
- Packages (all Pb-free)
- 16-pin SOIC (300 mil)
- 24-BGA (6 × 8 mm)
- 5 × 5 ball (FAB024) and 4 × 6 ball (FAC024) footprint options
- Known Good Die and Known Tested Die
Feature
- SPI clock polarity and phase modes 0 and 3
- Double data rate (DDR) option
- Common flash interface (CFI) data for configuration information
- Quad-input page programming (QPP) for slow clock systems
- Cycling endurance - 100000 program-erase cycles on any sector typical
- Data retention - 20 years data retention typical
- Spansion® 65nm Mirror-bit technology with Eclipse™ Architecture
- -40 to 85°C Industrial temperature range
(Picture:Pinout / Diagram)
