Feature
- Supports high performance system speed - 133 MHz
- (4.2 ns Clock-to-Data Access)
- ZBTTM Feature - No dead cycles between write and read
- cycles
- Internally synchronized registered outputs eliminate the
- need to control OE
- Single R/W (READ/WRITE) control pin
- Positive clock-edge triggered address, data, and control
- signal registers for fully pipelined applications
- 4-word burst capability (interleaved or linear)
- Individual byte write (BW1 - BW4) control (May tie active)
- Three chip enables for simple depth expansion
- Single 3.3V power supply (±5%)
- Available in 100-pin TQFP package
