The device feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input. The device provides sequential read operation on whole chip.After program/erase command is issued, auto program/erase algorithms which program/erase and verify the specified page or sector locations will be executed. Program command is executed on page (32 bytes) basis, and erase command is executes on sector, or block, or whole chip. To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit. When the device is not in operation and CS# is high, it is put in standby mode. The device utilizes Macronix proprietary memory cell, which reliably stores memory contents even after typical 100,000 program and erase cycles.
FEATURES：
GENERAL
• Serial Peripheral Interface compatible -- Mode 0 and Mode 3
• 512K: 524,288 x 1 bit structure
1M: 1,048,576 x 1 bit structure
• 16 Equal Sectors with 4K bytes each (512Kb)
32 Equal Sectors with 4K bytes each (1Mb)
- Any Sector can be erased individually
• 1 Equal Blocks with 64K byte each (512Kb)
2 Equal Blocks with 64K byte each (1Mb)
- Any Block can be erased individually
• Program Capability
- Byte base
- Page base (32 bytes)
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
PERFORMANCE
• Performance
- Fast Read: 45MHz serial clock
- Fast program time: 180us(typ.) and 650us(max.)/page
- Fast erase time: 40ms (typ.)/sector ; 1s (typ.)/block
• Low Power Consumption
- Low active read current: 5mA(max.) at 25MHz, 10mA(max.) at 45MHz
- Low active programming current: 8mA (typ.)
- Low active erase current: 10mA (typ.)
- Low standby current: 20uA (typ.)
- Deep power down current: 2uA (typ.)
• Typical 100,000 erase/program cycles
• 20 years data retention
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Block Lock protection
- The BP0~BP1 status bits defines the size of the area to be software protected against Program and Erase instructions
• Auto Erase and Auto Program Algorithm
- Automatically erases and verifies data at selected sector
- Automatically programs and verifies data at selected page by an internal algorithm that automatically times the
program pulse widths (Any page to be programed should have page in the erased state first)
• Status Register Feature
• Electronic Identification
- JEDEC 1-byte manufacturer ID and 2-bytes device ID
HARDWARE FEATURES
• SCLK Input
- Serial clock input
• SI Input
(Picture:Pinout / Diagram)
