• Multi I/O Support - Single I/O, Dual I/O and Quad I/O
• Auto Erase and Auto Program Algorithms
• Continuous Program mode
• Permanently fixed QE bit, QE=1; and 4 I/O mode is enabled
1. FEATURES
GENERAL
• Supports Serial Peripheral Interface -- Mode 0 and Mode 3
• 67,108,864 x 1 bit structure or 33,554,432 x 2 bits (two I/O mode) structure or 16,777,216 x 4 bits (four I/O mode) structure
• 2048 Equal Sectors with 4K bytes each
- Any Sector can be erased individually
• 256 Equal Blocks with 32K bytes each
- Any Block can be erased individually
• 128 Equal Blocks with 64K bytes each
- Any Block can be erased individually
• Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
• Permanent fixed QE bit, QE =1 and 4 I/O mode is enabled
PERFORMANCE
• High Performance VCC = 2.7~3.6V
- Normal read
- 50MHz
- Fast read
- 1 I/O: 104MHz with 8 dummy cycles
- 2 I/O: 86MHz with 4 dummy cycles for 2READ instruction
- 4 I/O: Up to 104MHz
- Configurable dummy cycle number for 4 I/O read operation
- Fast program time: 0.7ms(typ.) and 3ms(max.)/page (256-byte per page)
- Byte program time: 12us (typical)
- Continuous Program mode (automatically increase address under word program mode)
- Fast erase time: 30ms (typ.)/sector (4K-byte per sector) ; 0.25s(typ.) /block (64K-byte per block); 20s(typ.) / chip
• Low Power Consumption
- Low active read current: 19mA(max.) at 104MHz, 10mA(max.) at 33MHz
- Low active programming current: 15mA (typ.)
- Low active sector erase current: 10mA (typ.)
- Low standby current: 15uA (typ.)
- Deep power down current: 1uA (typ.)
• Typical 100,000 erase/program cycles
• 20 years data retention
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- BP0-BP3 block group protect
- Flexible individual block protect when OTP WPSEL=1
- Additional 4K bits secured OTP for unique identifier
• Auto Erase and Auto Program Algorithms
- Automatically erases and verifies data at selected sector
- Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse width (Any page to be programmed should have page in the erased state first.)
• Status Register Feature
• Electronic Identification
- JEDEC 1-byte Manufacturer ID and 2-byte Device ID
- RES command for 1-byte Device ID
- The REMS,REMS2, REMS4 commands for 1-byte Manufacturer ID and 1-byte Device ID
• Support Serial Flash Discoverable Parameters (SFDP) mode
HARDWARE FEATURES
• SCLK Input
- Serial clock input
• SI/SIO0
- Serial Data Input or Serial Data Input/Output for 2 x I/O mode and 4 x I/O mode
• SO/SIO1
- Serial Data Output or Serial Data Input/Output for 2 x I/O mode and 4 x I/O mode
• SIO2
- Serial data Input/Output for 4 x I/O mode
• SIO3
- Serial data Input/Output for 4 x I/O mode
• PACKAGE
- 16-pin SOP (300mil)
- 8-pin SOP (200mil)
- 8-pin VSOP (200mil)
- 8-WSON (6x5mm)
-12-ball WLCSP (Ball Diameter 0.30mm)
- All devices are RoHS Compliant and Halogen-free
2. GENERAL DESCRIPTION
MX25L6473E is 64Mb bits Serial Flash memory, which is configured as 8,388,608 x 8 internally. When it is in two or four I/O mode, the structure becomes 33,554,432 bits x 2 or 16,777,216 bits x 4.
MX25L6473E features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in single I/O mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input.
MX25L6473E, MXSMIO® (Serial Multi I/O) flash memory, provides sequential read operation on the whole chip and multi-I/O features.
When it is in dual or quad I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/ dummy bits input and data output.
After program/erase command is issued, auto program/erase algorithms which program/erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256 bytes) basis, or word basis for Continuous Program mode, and erase command is executed on 4K-byte sector, 32K-byte/64K-byte block, or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit. When the device is not in operation and CS# is high, it is put in standby mode.
The MX25L6473E utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles.
(Picture: Pinout)
