The 71T75802S100BGGI8 2.5V CMOS Synchronous SRAM organized as 1M x 18 (18 Megabit). It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71T75802S100BGGI8 contains data I/O, address and control signal registers.
Feature
- High performance system speed - 200 MHz (3.2 ns Clock-to-Data Access)
- ZBTTM Feature - No dead cycles between write and read cycles
- Internally synchronized output buffer enable eliminates the need to control OE
- Single R/W (READ/WRITE) control pin
- Positive clock-edge triggered address, data, and control signal registers for fully pipelined applications
- 4-word burst capability (interleaved or linear)
- Individual byte write (BW1 - BW4) control (May tie active)
- Three chip enables for simple depth expansion
- 2.5V power supply (±5%)
- 2.5V I/O Supply (VDDQ)
- Power down controlled by ZZ input
- Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)
- Available in 100-pin TQFP and 119-pin BGA packages
