OVERVIEW：
The LH28F008SAT-85 is a high-performance 8 Mbit (8,388,608 bit) memory organized as 1 Mbyte(1,048,576 bytes) of 8 bits each. Sixteen 64 KByte (65,536 byte) blocks are included on the LH28F008SAT-85.A memory map is shown in Figure 4 of this specification.A block erase operation erases one of the sixteen blocks of memory in typically 1.6 seconds, independent of the remaining blocks. Each block can be independently erased and written 100,000 cycles. Erase Suspend mode allows system soft- ware to suspend block erase to read data or execute code from any other block of the LH28F008SAT-85. The LH28F008SAT-85 is available in the 40-lead TSOP (Thin Small Outline Package,1.2 mm thick) package. Pinouts are shown in Figure 2 of this specification. The Command User Interface serves as the interface be- tween the microprocessor or microcontroller and the inter- nal operation of the LH28FO08SAT-85.
FEATURES：
·High-Density Symmetrically Blocked Architec-ture
-Sixteen 64KByte Blocks
·Extended Cycling Capability
-100，000 Block Erase Cycles
·1.6 Million Block Erase Cycles per Chip
·Automated Byte Write and Block Erase
-Command User Interface
-Status Register
·System Performance Enhancements
-RY/BY#Status Output
-Erase Suspend Capability
·Deep-Powerdown Mode
-10 uA lcc Maximum口
(Picture: Pinout)
