Feature
- Single power supply operation
- Dual chip enable inputs - Two CE# inputs control selection of each half of the memory space
- Data can be continuously read from one bank while executing erase/program functions in another bank
- Simultaneous read/write operation - Zero latency switching from write to read operations
- Secured silicon sector region
- Both top and bottom boot blocks in one device
- Manufactured on 110nm process technology
- Data retention - 20 years typical
- Cycling endurance - 1million cycles per sector typical
- High performance
- Power consumption
- Software command-set compatible with JEDEC 42.4 standard
- Erase suspend/erase resume
- Program suspend/program resume
- Unlock bypass program command
- Reduces overall programming time when issuing multiple program command sequences
- Ready/busy# pin - Provides a hardware method of detecting program or erase cycle completion
- Hardware reset pin - Hardware method to reset the device to reading array data
- WP#/ ACC input
- Persistent sector protection - Sectors can be locked and unlocked in-system at VCC level