Features
·High speed一15ns
·Fast tpoE
·Low active power一715mW
·Low standby power一220mW
·CMOS for optimum speed/power
·Easy memory expansion with CE1，CE2，and OE features
·TTL-compatible inputs and outputs
·Automatic power-down when deselected
Functional Description
The CY7C185-35PC is a high-performance CMOS static RAM orga-nized as 8192 words by 8 bits.Easy memory expansion is
provided by an active LOW chip enable(CE1), an active HIGH chip enable(CE2), and active LOW output enable (OE) and three-state drivers. This device has an automatic power-down feature(CE1or CE2), reducing the power consumption by 70%
when deselected. The CY7C185-35PC is in a standard 300-mil-wide DIPSOJ, or SOIC package.
An active LOW write enable signal(WE) controls the writ-ing/reading operation of the memory. When CE1and WE in-puts are both LOW and CEe is HIGH, data on the eight data input/output pins(I/Oo through I/O7) is written into the memory location addressed by the address present on the address pins(Ao through Ai2). Reading the device is accomplished bys selecting the device and enabling the outputs, CE1 and OE active LOW, CE, active HIGH, while WE remains inactive or HIGH. Under these conditions, the contents of the location ad-dressed by the information on address pins are present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable
(WE) is HIGH.A die coat is used to insure alpha immunity.
Feature
• High speed
— 15 ns
• Fast tDOE
• Low active power
— 715 mW
• Low standby power
— 220 mW
• CMOS for optimum speed/power
• Easy memory expansion with CE1, CE2, and OE
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
(Picture:Pinout / Diagram)
