TC7116CPL

The TC7116CPL is a 3-1/2-digit CMOS Analog-to-digital Converter (ADC) containing all the active components necessary to construct a 0.05% resolution measurement system. Seven-segment decoders, polarity and digit drivers, voltage reference and clock circuit are integrated on-chip. This device incorporates a display hold (HLDR) function. The displayed reading remains indefinitely, as long as HLDR is held high. Conversions continue, but output data display latches are not updated. The reference low input (VREF-) is not available, as it is with the TC7106/7107. VREF- is tied internally to analog common in the TC7116A/7117A devices. It reduces linearity error to less than 1 count. High-impedance differential inputs offer 1pA leakage current and a 10¹²R input impedance. The 15µVP-P noise performance enables a rock solid reading. The auto-zero cycle ensures a zero display reading with a 0V input.

Feature