The UJA1023 is a stand-alone Local Interconnect Network (LIN) I/O slave that replaces basic components commonly used in electronic control units for input and output handling. The UJA1023 contains a LIN 2.0 controller, an integrated LIN transceiver which is LIN 2.0 / SAE J2602 compliant and LIN 1.3 compatible, a 30 kΩ termination resistor necessary for LIN-slaves, and eight I/O ports which are configurable via the LIN bus.
An automatic bit rate synchronization circuit adapts to any (master) bit rate between 1 kbit/s and 20 kbit/s. For this, an oscillator is integrated.
The LIN protocol will be handled autonomously and both Node Address (NAD) and LIN frame Identifier (ID) programming will be done by a master request and an optional slave response message in combination with a daisy chain or plug coding function.
The eight bidirectional I/O pins are configurable via LIN bus messages and can have the following functions:
- Input:
- Standard input pin
- Local wake-up
- Edge capturing on falling, rising or both edges
- Analog input pin
- Switch matrix (in combination with output pins
- Output:
- Standard output pin as high-side driver, low-side driver or push-pull driver
- Cyclic sense mode for local wake-up
- PWM mode, for example, for back light illumination
- Switch matrix (in combination with input pins)
On entering a low-power mode it is possible to hold the last output state or to change over to a user programmable output state. In case of a failure (e.g. LIN bus short to ground) the output changes over to a user programmable limp home output state and the low-power Limp home mode will be entered.
Due to the advanced low-power behavior the power consumption of the UJA1023 in low-power mode is minimal.
Feature
- Automatic bit rate synchronization to any (master) bit rate between 1 kbit/s and 20 kbit/s
- Integrated LIN 2.0 / SAE J2602 transceiver (including 30 kΩ termination resistor)
- Eight bidirectional I/O pins
- 4 x 2, 4 x 3, or 4 x 4 switch matrix to support reading and supplying a maximum number of 16 switches
- Outputs configurable as high-side and/or low-side driver and as cyclic or PWM driver
- 8-bit ADC
- Advanced low-power behavior
- On-chip oscillator
- Node Address (NAD) configuration via daisy chain or plug coding
- Inputs supporting local wake-up and edge capturing
- Configurable Sleep mode
- Limp home configuration in case of error conditions
- Very low electromagnetic emission
- High immunity against electromagnetic interference
- Bus line protected in accordance with ISO 7637
- Extended ambient temperature range (-40 Cel to +125 Cel)
