The SC16C754BIB80,551 is a quad Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow control, and data rates up to 5 Mbit/s (3.3 V and 5 V). The SC16C754BIB80,551 offers enhanced features. It has a Transmission Control Register (TCR) that stores receiver FIFO threshold levels to start/stop transmission during hardware and software flow control. With the FIFO Ready (FIFO Rdy) register, the software gets the status of TXRDY/RXRDYfor all four ports in one access. On-chip status registers provide the user with error indications, operational status, and modem interface control. System interrupts may be tailored to meet user requirements. An internal loopback capability allows on-board diagnostics.
The UART transmits data, sent to it over the peripheral 8-bit bus, on the TX signal and receives characters on the RX signal. Characters can be programmed to be 5, 6, 7, or 8 bits. The UART has a 64-byte receive FIFO and transmit FIFO and can be programmed to interrupt at different trigger levels. The UART generates its own desired baud rate based upon a programmable divisor and its input clock. It can transmit even, odd, or no parity and 1, 1.5, or 2 stop bits. The receiver can detect break, idle, or framing errors, FIFO overflow, and parity errors. The transmitter can detect FIFO underflow. The UART also contains a software interface for modem control operations, and has software flow control and hardware flow control capabilities.
The SC16C754BIB80,551 is available in plastic LQFP64, LQFP80 and PLCC68 packages.
Feature
- 4 channel UART
- 5 V, 3.3 V and 2.5 V operation
- Pin compatible with SC16C654IA68, TL16C754, and SC16C554IA68 with additional enhancements, and software compatible with TL16C754
- Up to 5 Mbit/s data rate (at 3.3 V and 5 V; at 2.5 V maximum data rate is 3 Mbit/s)
- 5 V tolerant on input only pins
- 64-byte transmit FIFO
- 64-byte receive FIFO with error flags
- Industrial temperature range (-40 Cel to +85 Cel)
- Programmable and selectable transmit and receive FIFO trigger levels for DMA and interrupt generation
- Software (Xon/Xoff)/hardware (RTS/CTS) flow control
- Programmable Xon/Xoff characters
- Programmable auto-RTS and auto-CTS
- Optional data flow resume by Xon any character
- DMA signalling capability for both received and transmitted data
- Supports 5 V, 3.3 V and 2.5 V operation
- Software selectable baud rate generator
- Prescaler provides additional divide-by-4 function
- Fast data bus access time
- Programmable Sleep mode
- Programmable serial interface characteristics
- 5, 6, 7, or 8-bit characters
- Even, odd, or no-parity bit generation and detection
- 1, 1.5, or 2 stop bit generation
- False start bit detection
- Complete status reporting capabilities in both normal and Sleep mode
- Line break generation and detection
- Internal test and loopback capabilities
- Fully prioritized interrupt system controls
- Modem control functions (CTS, RTS, DSR, DTR, RI, and CD)
- Sleep mode
