The 9DBV0831AKILF is an 8-output very low power buffer for 100MHz PCIe Gen1, Gen2 and Gen3 applications. It can also be used for 50M or 125M Ethernet Applications via software frequency selection. The device has 8 output enables for clock management, and 3 selectable SMBus addresses.
Feature
- 1.8 V operation: minimal power consumption
- Outputs can optionally be supplied from any voltage between 1.05 V and 1.8 V; maximum power savings
- OE# pins: support DIF power management
- HCSL compatible differential input: can be driven by common clock sources
- LP-HCSL differential clock outputs: reduced power and board space
- Programmable slew rate for each output: allows tuning for various line lengths
- Programmable output amplitude: allows tuning for various application environments
- Pin/software selectable PLL bandwidth and PLL Bypass: minimize phase jitter for each application
- Outputs blocked until PLL is locked: clean system start-up
- Software selectable 50 MHz or 125 MHz PLL operation: useful for Ethernet Applications
- Configuration can be accomplished with strapping pins: SMBus interface not required for device control
- 3.3 V tolerant SMBus interface works with legacy controllers
- Space-saving6x6 mm48-pin VFQFPN: minimal board space
- Selectable SMBus addresses: multiple devices can easily share an SMBus segment
