Feature
- PCIe Gen1–5 CC-compliant
- Supports PCIe SRIS and SRNS clocking
- Integrated terminations for 100Ω and 85Ω systems save 4 resistors per output
- Pin-selectable SRnS 0%, CC 0% and CC/SRIS -0.5% spread
- SMBus-selectable CC/SRIS -0.25% spread
- One 3.3V LVCMOS REF output with Wake-On-LAN (WOL) support
- Easy AC-coupling to other logic families, see IDT application note .
- Space saving 6 × 6 mm 48-VFQFPN
(Picture: Pinout)