The ispXPLD 5000MX family represents a new class of device, referred to as the eXpanded Programmable Logic Devices (XPLDs). These devices extend the capability of Lattice’s popular SuperWIDE ispMACH 5000 architecture by providing flexible memory capability. The family supports single- or dual-port SRAM, FIFO, and ternary CAM operation. Extra logic has also been included to allow efficient implementation of arithmetic functions. In addition, sysCLOCK PLLs and sysIO interfaces provide support for the system-level needs of designers.
The devices provide designers with a convenient one-chip solution that provides logic availability at boot-up, design security, and extreme reconfigurability. The use of advanced process technology provides industry-leading performance with combinatorial propagation delay as low as 4.0ns, 2.8ns clock-to-out delay, 2.2ns set-up time, and operating frequency up to 300MHz. This performance is coupled with low static and dynamic power consumption. The ispXPLD 5000MX architecture provides predictable deterministic timing.
The availability of 3.3, 2.5 and 1.8V versions of these devices along with the flexibility of the sysIO interface helps users meet the challenge of today’s mixed voltage designs. Inputs can be safely driven up to 5.5V when an I/O bank is configured for 3.3V operation, making this family 5V tolerant. Boundary scan testability further eases integration into today’s complex systems. A variety of density and package options increase the likelihood of a good fit for a particular application. Table 1 shows the members of the ispXPLD 5000MX family.
Feature
■ Flexible Multi-Function Block (MFB) Architecture
• SuperWIDE™ logic (up to 136 inputs)
• Arithmetic capability
• Single- or Dual-port SRAM
• FIFO
• Ternary CAM
■ sysCLOCK™ PLL Timing Control
• Multiply and divide between 1 and 32
• Clock shifting capability
• External feedback capability
■ sysIO™ Interfaces
• LVCMOS 1.8, 2.5, 3.3V
– Programmable impedance
– Hot-socketing
– Flexible bus-maintenance (Pull-up, pulldown, bus-keeper, or none)
– Open drain operation
• SSTL 2, 3 (I & II)
• HSTL (I, III, IV)
• PCI 3.3
• GTL+
• LVDS
• LVPECL
• LVTTL
■ Expanded In-System Programmability (ispXP™)
• Instant-on capability
• Single chip convenience
• In-System Programmable via IEEE 1532 Interface
• Infinitely reconfigurable via IEEE 1532 or sysCONFIG™ microprocessor interface
• Design security
■ High Speed Operation
• 4.0ns pin-to-pin delays, 300MHz fMAX
• Deterministic timing
■ Low Power Consumption
• Typical static power: 20 to 50mA (1.8V), 30 to 60mA (2.5/3.3V)
• 1.8V core for low dynamic power
■ Easy System Integration
• 3.3V (5000MV), 2.5V (5000MB) and 1.8V (5000MC) power supply operation
• 5V tolerant I/O for LVCMOS 3.3 and LVTTL interfaces
• IEEE 1149.1 interface for boundary scan testing
• sysIO quick configuration
• Density migration
• Multiple density and package options
• PQFP and fine pitch BGA packaging
• Lead-free package options
