The Virtex-E FPGA family delivers high-performance, high-capacity programmable logic solutions. Dramatic increases in silicon efficiency result from optimizing the new architecture for place-and-route efficiency and exploiting an aggressive 6-layer metal 0.18 μm CMOS process. These advances make Virtex-E FPGAs powerful and flexible alternatives to mask-programmed gate arrays. The Virtex-E family includes the nine members in Table 1.
Building on experience gained from Virtex FPGAs, the Virtex-E family is an evolutionary step forward in programmable logic design. Combining a wide variety of programmable system features, a rich hierarchy of fast, flexible interconnect resources, and advanced process technology, the Virtex-E family delivers a high-speed and high-capacity programmable logic solution that enhances design flexibility while reducing time-to-market.
Table 1: Virtex-E Field-Programmable Gate Array Family Members
DeviceSystem GatesLogic GatesCLB ArrayLogic CellsDifferential I/O PairsUser I/OBlockRAM BitsDistributed RAM BitsXCV50E71,69320,73616 x 241,7288317665,53624,576XCV100E128,23632,40020 x 302,7008319681,92038,400XCV200E306,39363,50428 x 425,292119284114,68875,264XCV300E411,95582,94432 x 486,912137316131,07298,304XCV400E569,952129,60040 x 6010,800183404163,840153,600XCV600E985,882186,62448 x 7215,552247512294,912221,184XCV1000E1,569,178331,77664 x 9627,648281660393,216393,216XCV1600E2,188,742419,90472 x 10834,992344724589,824497,664XCV2000E2,541,952518,40080 x 12043,200344804655,360614,400XCV2600E3,263,755685,58492 x 13857,132344804753,664812,544XCV3200E4,074,387876,096104 x 15673,008344804851,9681,038,336
Feature
RF Data Converter Subsystem Overview
Most Zynq UltraScale+ RFSoCs include an RF data converter subsystem, which contains multiple radio frequency analog to digital converters (RF-ADCs) and multiple radio frequency digital to analog converters (RF-DACs). The high-precision, high-speed, power efficient RF-ADCs and RF-DACs can be individually configured for real data or can be configured in pairs for real and imaginary I/Q data.
Soft Decision Forward Error Correction (SD-FEC) Overview
Some Zynq UltraScale+ RFSoCs include highly flexible soft-decision FEC blocks for decoding and encoding data as a means to control errors in data transmission over unreliable or noisy communication channels. The SD-FEC blocks support low-density parity check (LDPC) decode/encode and Turbo decode for use in 5G wireless, backhaul, DOCSIS, and LTE applications.
Processing System Overview
Zynq UltraScale+ MPSoCs and RFSoCs feature dual and quad core variants of the Arm Cortex-A53 (APU) with dual-core Arm Cortex-R5F (RPU) processing system (PS). Some devices also include a dedicated Arm Mali™-400 MP2 graphics processing unit (GPU).
