Microchip Technology dsPIC33CH Dual Core Digital Signal Controllers combine two dsPIC DSC cores into a single chip. The dsPIC33CH Controllers have one core that is designed to function as a master while the other is designed as a slave. The slave core is useful for executing dedicated, time-critical control code while the master core is busy running the user interface, system monitoring, and communications functions, customized for the end application.
Feature
- Operating Conditions
- 3V to 3.6V, -40°C to +150°C
- Core: Dual 16-Bit dsPIC33CH CPUs
- Master Core 90 MIPS and Slave Core 100 MIPS Operation
- Independent Peripherals for Master Core and Slave Core
- Configurable Shared Resources for Master Core and Slave Core
- Fast 6-Cycle Divide
- Message Boxes and FIFO to Communicate Between Master and Slave (MSI)
- Code Efficient (C and Assembly) Architecture
- 40-Bit Wide Accumulators
- Single-Cycle (MAC/MPY) with Dual Data Fetch
- Single-Cycle, Mixed-Sign MUL Plus Hardware Divide
- 32-Bit Multiply Support
- Five Sets of Interrupt Context Selected Registers and Accumulators per Core for Fast Interrupt Response
- Zero Overhead Looping
- High Performance Peripherals for Real Time Control
- 4 x 12-bit 3.5 MSPS ADCs
- High Speed PWMs with 250ps resolution, 12 Ch
- Optimized for high-performance digital power, motor control and applications requiring sophisticated algorithms
- Master Core features
- Core Frequency 90 MIPS @ 180 MHz
- Internal Data RAM: 16 Kbytes
- 16-Bit Timer: 1
- DMA: 6
- SCCP (Capture/Compare/Timer): 8
- UART: 2
- SPI/I2S: 2
- I2C: 2
- CAN Flexible Data-Rate (FD): 1
- SENT: 2
- CRC: 1
- QEI: 1
- PTG:1
- CLC: 4
- 16-Bit High-Speed (250ps) PWM: 4
- 12-bit, 3.5 Msps ADC: 1
- Digital Comparator: 4
- 12-Bit DAC/Analog CMP Module: 1
- Watchdog Timer: 1
- Deadman Timer: 1
- Breakpoints: 3 complex, 5 simple
- Oscillator: 1
- Slave Core features
- Core Frequency 100 MIPS @ 200 MHz
- Program Memory: 24 Kbytes (PRAM) Dual Partition with LiveUpdate
- Internal Data RAM: 4 Kbytes
- 16-Bit Timer: 1
- DMA: 2
- SCCP (Capture/Compare/Timer): 4
- UART: 1
- SPI/I2S: 1
- I2C: 1
- QEI: 1
- CLC: 4
- 16-Bit High-Speed (250ps) PWM: 8
- 12-bit, 3.5 Msps ADC: 3
- Digital Comparator: 4
- 12-Bit DAC/Analog CMP Module: 3
- Watchdog Timer: 1
- Breakpoints: 1 complex, 2 simple
- Oscillator: 1
- Clock Management
- Internal Oscillator
- Programmable PLLs and Oscillator Clock Sources
- Master Reference Clock Output
- Slave Reference Clock Output
- Fail-Safe Clock Monitor (FSCM)
- Fast Wake-up and Start-up
- Backup Internal Oscillator
- LPRC Oscillator
- Power Management
- Low-Power Management Modes (Sleep, Idle, Doze)
- Integrated Power-on Reset and Brown-out Reset
- Debugger Development Support
- In-Circuit and In-Application Programming
- Simultaneous Debugging Support for Master and Slave Cores
- Master Only Debug and Slave Only Debug Support
- IEEE 1149.2 Compatible (JTAG) Boundary Scan
- Trace Buffer and Run-Time Watch
- Functional Safety support (ISO26262)
- ASIL-B & ASIL-C focused applications
- FMEDA, Diagnostic Software and Functional Safety manual available under NDA upon request to your sales office
- Functional Safety hardware features
- Multiple redundant clock sources
- I/O Port read-back
- Analog peripherals redundancies
- Windowed Watchdog Timer
- RAM BIST
- Hardware traps
- SFR locks
- Write protection
- Shadow working registers
