The ADSP-TS101SAB1-100 is the first member of the TigerSHARC Processor family. Targeted at numerous signal processing applications that rely on multiple processors working together to execute computationally-intensive real-time functions, ADI’s TigerSHARC processor is well-suited to video and communication markets, including the 3G cellular and broadband wireless base stations, as well as defense, medical imaging, industrial instrumentation. The ADSP-TS101SAB1-100 features a static superscaler architecture which combines RISC, VLIW and standard DSP functionality. Native support of fixed and floating point data types, coupled with the leading edge multiprocessing capabilities allows the TigerSHARC processor to offer unrivaled DSP performance. At a 300 MHz clock rate, the ADSP-TS101SAB1-100 offers the industry’s highest 16-bit fixed-point performance and a 32-bit floating 1024-point complex FFT time of 32.5 microseconds.
ADSP-TS101SAB1-100 Performance:
The ADSP-TS101SAB1-100 is available in both 19mm X 19mm and 27mm X 27mm inexpensive, plastic ball-grid array packages. The TigerSHARC is available for general purpose sampling today.
Feature
- Static Superscalar architecture which supports 1, 8, 16 and 32-bit fixed point as well as floating point data processing
- High performance 300 MHz, 3.3 ns instruction rate DSP core
- 6 Mbit on-chip SRAM internally organized in three banks with user-defined partitioning
- 14 channel, zero overhead DMA controller
- Enhanced communications instruction set for wireless infrastructure applications allows for the TigerSHARC to offer complete base band processing
- Three internal 128-bit wide internal buses providing a total memory bandwidth of 14.4 Gbytes per second
- Software radio approach allows for the adoption of a single platform for multiple wireless telecommunication standards
- Single instruction multiple-data (SIMD) operation supported by two computation blocks each with an ALU, multiplier, shifter and 32-word register file
- Assembly and C language programmability
