AS7C1026B-15JIN

The AS7C1026B-15JIN is a 5V 64k x 16-bit CMOS Static Random Access Memory (SRAM) organized as 65536 words x 16-bit. It offers 10/12/15/20ns address access time, 5/6/7/8ns output enable access time high speed. It features easy memory expansion with CE, OE inputs. It is designed for memory applications where fast data access, low power and simple interfacing are desired. When CE is high, the device enters standby mode. If inputs are still toggling, the device will consume ISB power. If the bus is static, then full standby power is reached. For example, the AS7C1026B is guaranteed not to exceed 55mW under nominal full standby conditions. A write cycle is accomplished by asserting write enable and chip enable. Data on the input pins I/O0 through I/O15 is written on the rising edge of WE or CE. To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable or write enable.

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