• Clock frequency: 200, 166, 143, 133 MHz
• Fully synchronous; all signals referenced to a positive clock edge
• Internal bank for hiding row access/precharge
• Single 3.3V power supply
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence: Sequential/Interleave
• Self refresh modes
• Auto refresh (CBR)
• 4096 refresh cycles every 64 ms (Com, Ind, A1 grade) or 16ms (A2 grade)
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write operations capability
• Burst termination by burst stop and precharge command
DESCRIPTION
The 64Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V memory systems containing 67,108,864 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 16,777,216-bit bank is organized as 4,096 rows by 256 columns by 16 bits.
The 64Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL compatible.
The 64Mb SDRAM has the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during burst access.
Feature
- Synchronous with 3.3V Power Supply
- LVTTL Interface
- Programmable Burst Length (1, 2, 4, 8, Full Page)
- Sequential/Interleave Programmable Burst Sequence
- Self Refresh and Auto Refresh Modes
- Random Column Address Every Clock Cycle
- Programmable CAS Latency (2, 3 Clocks)
- Burst Read/Write and Burst Read/Single Write
- Long-term Support
- 200, 166, 143 and 133MHz Clock Frequency
- Fully Synchronous, All Signals Referenced to a Positive Clock Edge
- Internal Bank for Hiding Row Access/Pre-charge
- 4096 Refresh Cycles Every 64ms (Com, Ind, A1 Grade) or 16ms (A2 Grade)
(Picture:Pinout / Diagram)
