MT48LC32M16A2TG-75:CTR

Alliance Memory 512Mb SDR SDRAM Series are high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. They are internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4's 134,217,728-bit banks is organized as 8192 rows by 4096 columns by 4 bits. Each of the x8's 134,217,728-bit banks is organized as 8192 rows by 2048 columns by 8 bits. Each of the x16's 134,217,728-bit banks is organized as 8192 rows by 1024 columns by 16 bits.