The Micron Parallel NOR Flash memory is the latest generation of Flash memory devices. Benefits include more density in less space, high-speed interface device, and support for code and data storage. Features include high-performance synchronous-burst read mode, fast asynchronous access times, low power, flexible security options, and three industry-standard package choices. The product family is manufactured using Micron 65nm process technology.
The NOR Flash device provides high performance at low voltage on a 16-bit data bus. Individually erasable memory blocks are sized for optimum code and data storage.
Upon initial power up or return from reset, the device defaults to asynchronous pagemode read. Configuring the read configuration register enables synchronous burstmode reads. In synchronous burst mode, output data is synchronized with a user-supplied clock signal. A WAIT signal provides easy CPU-to-flash memory synchronization.
Feature
• High performance
– 100ns initial access for Easy BGA
– 110ns initial access for TSOP
– 25ns 16-word asychronous page read mode
– 52 MHz (Easy BGA) with zero WAIT states and 17ns clock-to-data output synchronous burst read mode
– 4-, 8-, 16-, and continuous word options for burst mode
– Buffered enhanced factory programming (BEFP) at 2 MB/s (TYP) using a 512-word buffer
– 1.8V buffered programming at 1.14 MB/s (TYP) using a 512-word buffer
• Architecture
– MLC: highest density at lowest cost
– Asymmetrically blocked architecture
– Four 32KB parameter blocks: top or bottom configuration
– 128KB main blocks
– Blank check to verify an erased block
