The 66AK2L06XCMS KeyStone SoC is a member of the C66x family based on TI's new KeyStone II Multicore SoC Architecture and is a low-power solution with integrated JESD204B lanes that meets the more stringent power, size, and cost requirements of applications requiring connectivity with ADC and DAC based applications. The device’s ARM and DSP cores deliver exceptional processing power on platforms requiring high signal and control processing.
TI’s KeyStone II Architecture provides a programmable platform integrating various subsystems (ARM CorePac, C66x CorePacs, IP network, Digital Front End, and FFT processing) and uses a queue-based communication system that allows the SoC resources to operate efficiently and seamlessly. This unique SoC architecture also includes a TeraNet switch that enables the wide mix of system elements, from programmable cores to dedicated coprocessors and high-speed IO, to each operate at maximum efficiency with no blocking or stalling.
The addition of the ARM CorePac in the 66AK2L06XCMS device enables the ability for complex control code processing on-chip. Operations such as housekeeping and management processing can be performed with the Cortex-A15 processor.
TI’s new C66x core launches a new era of DSP technology by combining fixed-point and floating-point computational capability in the processor without sacrificing speed, size, or power consumption. The raw computational performance is an industry-leading 38.4 GMACS/core and 19.2 Gflops/core (@ 1.2 GHz operating frequency). The C66x is also 100% backward compatible with software for C64x+ devices. The C66x CorePac incorporates 90 new instructions targeted for floating point (FPi) and vector math oriented (VPi) processing.
The 66AK2L06XCMS contains many coprocessors to offload the bulk of the processing demands of higher layers of application. This keeps the cores free for algorithms and other differentiating functions. The SoC contains multiple copies of key coprocessors such as the FFTC. The architectural elements of the SoC (Multicore Navigator) ensure that data is processed without any CPU intervention or overhead, allowing the system to make optimal use of its resources.
TI’s scalable multicore SoC architecture solutions provide developers with a range of software-compatible and hardware-compatible devices to minimize development time and maximize reuse.
The 66AK2L06XCMS device has a complete set of development tools that includes: a C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows and Linux debugger interface for visibility into source code execution.
Feature
- Four TMS320C66x DSP Core Subsystems (C66x
CorePacs), Each With- 1.0 GHz or 1.2 GHz C66x Fixed/Floating-Point
DSP Core- 38.4 GMacs/Core for Fixed Point @ 1.2 GHz
- 19.2 GFlops/Core for Floating Point @ 1.2
GHz
- Memory
- 32K Byte L1P Per CorePac
- 32K Byte L1D PerCorePac
- 1024K Byte Local L2 Per CorePac
- 1.0 GHz or 1.2 GHz C66x Fixed/Floating-Point
- ARM CorePac
- Two ARM Cortex-A15 MPCore Processors
at Up to 1.2 GHz - 1MB L2 Cache Memory Shared by Two ARM
Cores - Full Implementation of ARMv7-A Architecture
Instruction Set - 32KB L1 Instruction and Data Caches per Core
- AMBA 4.0 AXI Coherency Extension (ACE)
Master Port, Connected to MSMC for Low
Latency Access to Shared MSMC SRAM
- Two ARM Cortex-A15 MPCore Processors
- Multicore Shared Memory Controller (MSMC)
- 2 MB SRAM Memory Shared by Four DSP
CorePacs and One ARM CorePac - Memory Protection Unit for Both MSM SRAM
and DDR3_EMIF
- 2 MB SRAM Memory Shared by Four DSP
- On-chip Standalone RAM (OSR) - 1MB On-Chip
SRAM for Additional Shared Memory - Hardware Coprocessors
- Two Fast Fourier Transform Coprocessors
- Support Up to 1200 Msps at FFT Size 1024
- Support Max FFT Size 8192
- Two Fast Fourier Transform Coprocessors
- Multicore Navigator
- 8k Multi-Purpose Hardware Queues with Queue
Manager - Packet-Based DMA for Zero-Overhead
Transfers
- 8k Multi-Purpose Hardware Queues with Queue
- Network Coprocessor
- Packet Accelerator Enables Support for
- 1 Gbps Wire Speed Throughput at 1.5
MPackets Per Second
- 1 Gbps Wire Speed Throughput at 1.5
- Security AcceleratorEngine Enables Support for
- IPSec, SRTP, and SSL/TLS Security
- ECB, CBC, CTR, F8,CCM, GCM, HMAC,
CMAC, GMAC, AES, DES, 3DES, SHA-1,
SHA-2 (256-bit Hash), MD5 - Up to 6.4 Gbps IPSec
- Ethernet Subsystem
- Peripherals
- DigitalFront End (DFE) Subsystem
- Support up to Four Lane JESD204A/B (7.37
Gbps Line Rate Max.) Interface to Multiple
Data Converters - Integration of Digital Down/Up-Conversion
(DDC/DUC) Module
- Support up to Four Lane JESD204A/B (7.37
- IQNet Subsystem
- Transporting data streams to an integrated
Digital Front End (DFE)
- Transporting data streams to an integrated
- Two One-Lane PCIe Gen2 Interfaces
- Supports Up to 5 GBaud
- Three Enhanced Direct Memory Access (EDMA)
Controllers - 72-Bit DDR3 Interface, Speeds Up to 1600 MHz
- EMIF16 Interface
- USB 3.0 Interface
- USIM Interface
- Four UART Interfaces
- Three I2C Interfaces
- 64 GPIO Pins
- Three SPI Interfaces
- Semaphore Module
- Fourteen 64-Bit Timers
- DigitalFront End (DFE) Subsystem
- Commercial Case Temperature:
- 0°C to 100°C
- Extended Case Temperature:
- –40°C to 100°C
- Packet Accelerator Enables Support for
