This 40,000 to 50,000-gate coprocessor is a fully PCI-compliant, SRAM-based FPGA with distributed 10-ns programmable synchronous/asynchronous, dual-port/single-port SRAM, 8 global clocks, Cache Logic® ability (partially or fully reconfigurable without loss of data), and automatic component generators. It has a 384 I/O count and supports a 5-V design. It can be used as a coprocessor for high-speed (DSP/processor-based) designs by implementing a variety of computation intensive, arithmetic functions. It is designed to quickly implement high-performance, large gate count designs through the use of synthesis and schematic-based tools used on a PC or Sun platform.
This 40,000 to 50,000-gate coprocessor is a fully PCI-compliant, SRAM-based FPGA with distributed 10-ns programmable synchronous/asynchronous, dual-port/single-port SRAM, 8 global clocks, Cache Logic® ability (partially or fully reconfigurable without loss of data), and automatic component generators. It has a 384 I/O count and supports a 5-V design. It can be used as a coprocessor for high-speed (DSP/processor-based) designs by implementing a variety of computation intensive, arithmetic functions. It is designed to quickly implement high-performance, large gate count designs through the use of synthesis and schematic-based tools used on a PC or Sun platform.
Feature
• Ultra High Performance
– System Speeds to 100 MHz
– Array Multipliers > 50 MHz
– 10 ns Flexible SRAM
– Internal Tri-state Capability in Each Cell
• FreeRAM™
– Flexible, Single/Dual Port, Synchronous/Asynchronous 10 ns SRAM
– 2,048 - 18,432 Bits of Distributed SRAM Independent of Logic Cells
• 128 - 384 PCI Compliant I/Os
– 3V/5V Capability
– Programmable Output Drive
– Fast, Flexible Array Access Facilitates Pin Locking
– Pin-compatible with XC4000, XC5200 FPGAs
• 8 Global Clocks
– Fast, Low Skew Clock Distribution
– Programmable Rising/Falling Edge Transitions
– Distributed Clock Shutdown Capability for Low Power Management
– Global Reset/Asynchronous Reset Options
– 4 Additional Dedicated PCI Clocks
• Cache Logic® Dynamic Full/Partial Re-configurability In-System
– Unlimited Re-programmability via Serial or Parallel Modes
– Enables Adaptive Designs
– Enables Fast Vector Multiplier Updates
– QuickChange™ Tools for Fast, Easy Design Changes
• Pin-compatible Package Options
– Plastic Leaded Chip Carriers (PLCC)
– Thin, Plastic Quad Flat Packs (LQFP, TQFP, PQFP)
– Ball Grid Arrays (BGAs)
• Industry-standard Design Tools
– Seamless Integration (Libraries, Interface, Full Back-annotation) with Concept®, Everest, Exemplar™, Mentor®, OrCAD®, Synario™, Synopsys®, Verilog®, Veribest®, Viewlogic®, Synplicity®
– Timing Driven Placement & Routing
– Automatic/Interactive Multi-chip Partitioning
– Fast, Efficient Synthesis
– Over 75 Automatic Component Generators Create 1000s of Reusable, Fully Deterministic Logic and RAM Functions
• Intellectual Property Cores
– Fir Filters, UARTs, PCI, FFT and Other System Level Functions
• Easy Migration to Atmel Gate Arrays for High Volume Production
• Supply Voltage 5V for AT40K, and 3.3V for AT40KLV
