· High-performance read, program, and erase
-96ns initial read access
-108MHz with zero wait-state synchronous burst reads:7ns clock-to-data output
-133MHz with zero wait-state synchronous burst reads:5.5ns clock-to-data output
-8-,16-, and continuous-word synchronous-burst reads
-Programmable WAIT configuration
-Customer-configurable output driver impedance
-Buffered Programming:2.0 us/Word(TYP), 512Mb,65nm
-Block erase:0.9s per block(TYP)
-20us(TYP) program/erase suspend
·Architecture
-16-bit wide data bus
-Multilevel cell technology
-Symmetrically-blocked array architecture
-256KB erase blocks
-1Gb device:Eight 128Mb partitions
-512Mb device:Eight 64Mb partitions-256Mb device:Eight 32Mb partitions-READ-While-PROGRAM and READ-While-ERASE commands
-Status register for partition/device status
-Blank check feature
·Temperature Range
-Expanded temperature:-40℃ to+85℃
·JESD47H-compliant
-Minimum 100,000 ERASE cycles per block
-Data retention:20 years(TYP)
· Power
-Core voltage:1.7-2.0V
-I/O voltage:1.7-2.0V
-Standby current:60uA(TYP) for 512Mb,65nm
-Automatic power savings mode
-16-word synchronous-burst read current:23mA (TYP)@108 MHz;24mA(TYP)@133MHz
· Software
-Micron Flash data integrator(FDI) optimized
-Basic command set(BCS) and extended command set(ECS) compatible
-Common Flash interface(CFI) capable
· Security
-One-time programmable(OTP) space 64unique factory device identifier bits 2112 user-programmable OTP bits
-Absolute write protection: Vpp=GND
-Power-transition erase/program lockout
-Individual zero latency block locking
-Individual block lock-down
·Density and packaging
-256Mb,512Mb,and1Gb
-Address-data multiplexed and non-multiplexed interfaces
-64-Ball Easy BGA
General Description
Micron's 65nm device is the latest generation of StrataFlash® memory featuring flexible, multiple-partition, dual-operation architecture. The device provides high-performance, asynchronous read mode and synchronous-burst read mode using 1.8V low-voltage, multilevel cell (MLC) technology.
The multiple-partition architecture enables background programming or erasing to occur in one partition while code execution or data reads take place in another partition.
This dual-operation architecture also allows two processors to interleave code operations while PROGRAM and ERASE operations take place in the background. The multiple partitions allow flexibility for system designers to choose the size of the code and data segments.
The device is manufactured using 65nm process technologies and is available in industry-standard chip scale packaging.
(Picture:Pinout / Diagram)
